Design a 8 bit CPU ISA
Hello there. I am going to design a 8 bit CPU because I actually has design a 3 bit cpu before when I was in form 1. Although the cpu is barely working but it give me a nostalgia feeling. Now, I want to try to design a new CPU that is really working. Since I have some experience in operating system development and I usually use assembly language in AVR development, I can understand the mechanism of CPU quite easy now.
What is the characteristic of this CPU
Well, I have to accept the fact that I dont have a silicon factory to make a CPU. Luckily, it is 21 century now. Simulate a CPU in a CPU is a common thing nowaday. So, I am going to run this CPU in Logisim. If possible, I will it into Minecraft redstone computer.
However, redstone in Minecraft is difference from electronic in real life. The highest frequency redstone can get is 20Hz and the simulation size in Minecraft is 64 chunks. So, I have to do some adaptation to the CPU to make it can run well in Minecraft and here is the list:
- run on low clock frequency (1Hz)
- using RISC to reduce my brain cell damage when designing the cpu
- implement excution pipeline (if possible)
My custom architecture, LBK8
To make a working CPU, a good and optimized architecture is important. It can affect the performance and efficient of CPU greatly. Before I started to design my own architecture, I need to give it a fancy name. After some consideration, I named it LBK8.
Because this is my first cpu, so I am going to make it simple and only use 8 bit data bus and 8 bit address bus. For the instruction, I am going to fix it into 8 bit size and here is the structure of it:
| Oprand | Opcode | Description |
|---|---|---|
| 4 bit | 4 bit | 4 bit literal value |
| 2 bit (reg Y) 2 bit (reg X) | 4 bit | 2 register |
Here is the first list of instruction I think is necessary:
| Opcode | Instruction | Description | Operation |
|---|---|---|---|
| 0x0 | JMP | Jump to oprand | R -> PC |
| 0x1 | LLA | Load 4 bit oprand into lower nibble register A | R -> A |
| 0x2 | LHA | Shift register A to left 4 bit and add 4 bit oprand into register A | A << 4 A += R |
| 0x3 | MOV | Copy value of register X to register Y | X -> Y |
| 0x4 | MOV | Copy value of register A to RAM with address in oprand | A -> [R] |
| 0x5 | ADD | Add two register and store result into register Y | (X + Y) -> Y |
| 0x6 | SUB | Subtract two register and store result into register Y | (X - Y) -> Y |
| 0x7 | AND | Perform AND operation between two register and store result into register Y | (X & Y) -> Y |
| 0x8 | NOT | Perform NOT operation on register Y and store result into register Y | !Y -> Y |
| 0x9 | OR | Perform OR operation between two register and store result into register Y | (X or Y) -> Y |
| 0xA | CMP | Compare two register and result is fetchable in next instruction | cmp(X, Y) |
| 0xB | JE | Jump if E flag is up | if E, R -> PC |
| 0xC | JH | Jump if H flag is up | if H, R -> PC |
| 0xD | JL | Jump if L flag is up | if L, R -> PC |
| 0xE | HLT | Halt cpu by disconnect clock signal |